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high slew rate, wide bandwidth, jfet input operational amplifiers these devices are a new generation of high speed jfet input monolithic operational amplifiers. innovative design concepts along with jfet technology provide wide gain bandwidth product and high slew rate. wellmatched jfet input devices and advanced trim techniques ensure low input offset errors and bias currents. the all npn output stage features large output voltage swing, no deadband crossover distortion, high capacitive drive capability, excellent phase and gain margins, low open loop output impedance, and symmetrical source/sink ac frequency response. this series of devices is available in fully compensated or decompensated (a vcl 2) and is specified over a commercial temperature range. they are pin compatible with existing industry standard operational amplifiers, and allow the designer to easily upgrade the performance of existing designs. ? wide gain bandwidth: 8.0 mhz for fully compensated devices wide gain bandwidth: 16 mhz for decompensated devices ? high slew rate: 25 v/ m s for fully compensated devices high slew rate: 50 v/ m s for decompensated devices ? high input impedance: 10 12 w ? input offset voltage: 0.5 mv maximum (single amplifier) ? large output voltage swing: 14.7 v to +14 v for large output voltage swing: v cc /v ee = 15 v ? low open loop output impedance: 30 w @ 1.0 mhz ? low thd distortion: 0.01% ? excellent phase/gain margins: 55 /7.6 db for fully compensated devices ordering information op amp function fully compen- sated a vcl 2 compensated operating temperature range package single mc34081bd mc34080bd so8 single mc34081bp mc34080bp t a = 0 to +70 c plastic dip dual mc34082p mc34083bp plastic dip quad mc34084dw mc34085bdw t 0 to +70 c so16l quad mc34084p mc34085bp t a = 0 to +70 c plastic dip pin connections (quad, top view) 4 23 1 4 23 1 inputs 1 output 1 v cc inputs 2 output 2 inputs 1 output 1 v cc inputs 2 output 2 nc output 4 inputs 4 v ee inputs 3 output 3 output 4 inputs 4 v ee inputs 3 output 3 nc 1 2 3 4 5 6 710 11 12 13 14 15 16 8 9 1 2 3 4 5 6 78 9 10 11 12 13 14 - + - + + - + - - + - + + - + - on semiconductor ? semiconductor components industries, llc, 2002 march, 2002 rev. 1 1 publication order number: mc34080/d mc34080 thru mc34085 high performance jfet input operational amplifiers d suffix plastic package case 751 (so8) p suffix plastic package case 626 pin connections (single, top view) (dual, top view) - offset null noninv. input v ee inv. input v ee inputs 1 output 1 nc v cc output offset null inputs 2 output 2 v cc 1 2 3 4 8 7 6 5 + 1 2 3 4 8 7 6 5 + + 1 8 1 8 dw suffix plastic package case 751g (so16l) p suffix plastic package case 646 14 1 16 1
mc34080 thru mc34085 http://onsemi.com 2 maximum ratings rating symbol value unit supply voltage (from v cc to v ee ) v s +44 v input differential voltage range v idr (note 1) v input voltage range v ir (note 1) v output short circuit duration (note 2) t sc indefinite sec operating ambient temperature range t a 0 to +70 c operating junction temperature t j +125 c storage temperature range t stg 65 to +165 c notes: 1. either or both input voltages must not exceed the magnitude of v cc or v ee . 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded. *pins 1 & 5 (mc34080,081) should not be directly grounded or connected to v cc . inputs - + j1 j2 q1 v cc q6 r1 240 18 d2 r sc q7 c m q4 q3 q2 q8 q9 500 q10 r6 rm q11 d4 r3 1.0 k q5 c c c f 20 pf d3 v ee 200 m a output null adjust (mc34080, 081)* 50 m a 850 m a 5.0 pf 3.0 pf 100 m a 300 m a 50 m a 500 w r4 1.0 k d1 r7 66 k 700 r2 + + 1 5 representative schematic diagram (each amplifier)
mc34080 thru mc34085 http://onsemi.com 3 dc electrical characteristics (v cc = +15 v, v ee = 15 v, t a = t low to t high [note 3], unless otherwise noted.) characteristics symbol min typ max unit input offset voltage (note 4) single t a = +25 c t a = 0 to +70 c (mc34080b, mc34081b) dual t a = +25 c t a = 0 to +70 c (mc34082, mc34083) quad t a = +25 c t a = 0 to +70 c (mc34084, mc34085) v io e e e e e e 0.5 e 1.0 e 6.0 e 2.0 4.0 3.0 5.0 12 14 mv average temperature coefficient of offset voltage d v io / d t e 10 e m v/ c input bias current (v cm = 0 note 5) t a = +25 c t a = 0 to +70 c i ib e e 0.06 e 0.2 4.0 na input offset current (v cm = 0 note 5) t a = +25 c t a = 0 to +70 c i io e e 0.02 e 0.1 2.0 na large signal voltage gain (v o = 10 v, r l = 2.0 k) t a = +25 c t a = t low to t high a vol 25 15 80 e e e v/mv output voltage swing r l = 2.0 k, t a = +25 c r l = 10 k, t a = +25 c r l = 10 k, t a = t low to t high v oh 13.2 13.4 13.4 13.7 13.9 e e e e v r l = 2.0 k, t a = +25 c r l = 10 k, t a = +25 c r l = 10 k, t a = t low to t high v ol e e e 14.1 14.7 e 13.5 14.1 14.0 output short circuit current (t a = +25 c) input overdrive = 1.0 v, output to ground source sink i sc 20 20 31 28 e e ma input common mode voltage range t a = +25 c v icr (v ee +4.0) to (v cc 2.0) v common mode rejection ratio (r s 10 k, t a = +25 c) cmrr 70 90 e db power supply rejection ratio (r s = 100 w , t a = 25 c) psrr 70 86 e db power supply current single t a = +25 c t a = t low to t high dual t a = +25 c t a = t low to t high quad t a = +25 c t a = t low to t high i d e e e e e e 2.5 e 4.9 e 9.7 e 3.4 4.2 6.0 7.5 11 13 ma notes: (continued) 3. t low =0 c for mc34080b t high = +70 c for mc34080b 0 c for mc34081b +70 c for mc34081b 0 c for mc34084 +70 c for mc34084 0 c for mc34085 +70 c for mc34085 4. see application information for typical changes in input offset voltage due to solderability and temperature cycling. 5. limits at t a = +25 c are guaranteed by high temperature (t high ) testing.
mc34080 thru mc34085 http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = 15 v, t a = +25 c, unless otherwise noted.) characteristics symbol min typ max unit slew rate (v in = 10 v to +10 v, r l = 2.0 k w , c l = 100 pf) compensated a v = +1.0 a v = 1.0 decompensated a v = +2.0 a v = 1.0 sr 20 e 35 e 25 30 50 50 e e e e v/ m s settling time (10 v step, a v = 1.0) to 0.10% ( 1 / 2 lsb of 9bits) to 0.01% ( 1 / 2 lsb of 12bits) t s e e 0.72 1.6 e e m s gain bandwidth product (f = 200 khz) compensated decompensated gbw 6.0 12 8.0 16 e e mhz power bandwidth (r l = 2.0 k, v o = 20 v pp , thd = 5.0%) compensated a v = +1.0 decompensated a v = 1.0 bwp e e 400 800 e e khz phase margin (compensated) r l = 2.0 k r l = 2.0 k, c l = 100 pf f m e e 55 39 e e de- grees gain margin (compensated) r l = 2.0 k r l = 2.0 k, c l = 100 pf a m e e 7.6 4.5 e e db equivalent input noise voltage r s = 100 w , f = 1.0 khz e n e 30 e nv/ hz equivalent input noise current (f = 1.0 khz) i n e 0.01 e pa/ hz input capacitance c i e 5.0 e pf input resistance r i e 10 12 e w total harmonic distortion a v = +10, r l = 2.0 k, 2.0 v o 20 v pp , f = 10 khz thd e 0.05 e % channel separation (f = 10 khz) e e 120 e db open loop output impedance (f = 1.0 mhz) z o e 35 e w figure 1. input common mode voltage range versus temperature figure 2. input bias current versus temperature t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 v , input common mode voltage range (v) icr v ee v cc /v ee = 3.0 v to 22 v d v io = 5.0 ma v cc t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 i, input bias current (pa) ib v cc /v ee = 15 v v cm = 0 v 0 -1.0 3.0 2.0 1.0 0 100 k 10 k 1.0 k 100 10 1.0
mc34080 thru mc34085 http://onsemi.com 5 sink source v cc /v ee = 15 v r l 0.1 w d v in = 1.0 v v cc /v ee = +15 v r l to v cc t a = 25 c v ee v cc v cc /v ee = 15 v t a = 25 c v cc v ee v cc /v ee = +15 v to +22 v t a = 25 c v cc v ee sink source v o , output voltage swing (v pp ) figure 3. input bias current versus input common mode voltage figure 4. output voltage swing versus supply voltage figure 5. output saturation versus load current figure 6. output saturation vesus load resistance to ground figure 7. output saturation versus load resistance to v cc figure 8. output short circuit current versus temperature i ib -12 -8.0 -4.0 0 4.0 8.0 12 v ic , input common mode voltage (v) v cc /v ee = 15 v t a = 25 c 0 5.0 10 15 20 25 v cc |v ee |, supply voltage (v) r l = 10 k r l connected to ground t a = 25 c r l = 2.0 k 0 4.0 8.0 12 16 i l , load current ( ma) v sat 300 3.0 k 30 k 300 k r l , load resistance to ground ( w ) 300 3.0 k 30 k 300 k r l , load resistance to v cc ( w ) -55 -25 0 25 50 75 100 125 i, output short circuit current (ma) sc t a , ambient temperature ( c) , input bias current (pa) , output saturation voltage (v) v sat , output saturation voltage (v) v sat , output saturation voltage (v) 140 120 100 80 60 40 20 50 40 30 20 10 0 0 -1.0 -2.0 -3.0 1.0 0 0 -2.0 -4.0 2.0 1.0 0 0 -0.4 -0.8 2.0 1.0 0 40 30 10 0 20
mc34080 thru mc34085 http://onsemi.com 6 v cc /v ee = 15 v v cm = 0 v o = 0 d i o = 0.5 ma t a = 25 c decompensated units only a v = 1000 a v = 100 a v = 2.0 a v = 10 v o , output voltage swing (v pp ) figure 9. output impedance versus frequency figure 10. output impedance versus frequency figure 11. output voltage swing versus frequency figure 12. output distortion versus frequency figure 13. open loop voltage gain versus temperature z, output impedance () o w f, frequency (hz) 1.0 k 10 k 100 k 1.0 m 10 m a v = 10 v cc /v ee = 15 v v cm = 0 v o = 0 d i o = 0.5 ma t a = 25 c compensated units only a v = 1000 a v = 100 a v = 1000 a v = 1.0 z, output impedance () o w f, frequency (hz) 1.0 k 10 k 100 k 1.0 m 10 m 10 k 100 k 1.0 m 10 m f, frequency (hz) 10 100 1.0 k 10 k 100 k a v = 1.0* thd, output distortion (%) f, frequency (hz) a v = 10 v cc /v ee = 15 v v o = 2.0 v pp r l = 2.0 k t a = 25 c *compensated units only -55 -25 0 25 75 100 50 125 vol a, open loop voltage gain (db normalized) t a , ambient temperature ( c) v cc /v ee = 15 v v o = -10 v to +10 v r l = 10 k f 10 hz 80 60 40 20 0 80 60 40 20 0 28 24 20 16 12 8.0 4.0 0 0.5 0.4 0.3 0.2 0.1 0 1.08 1.04 1.00 0.96 0.92 v cc /v ee = 15 v r l = 2.0 k thd = 1.0% t a = 25 c decompensated units a v = -1.0 compensated units a v = +1.0 a v = 1000 a v = 100
mc34080 thru mc34085 http://onsemi.com 7 1 gain, r l = 2.0 k 2 gain, r l = 2.0 k, c l = 100 pf 3 phase, r l = 2.0 k 4 phase, r l = 2.0 k, c l = 100 pf decompensated units only v cc /v ee = 15 v v o = 0 v t a = 25 c phase margin = 43 gain margin = 5.5 db figure 14. open loop voltage gain and phase versus frequency figure 15. open loop voltage gain and phase versus frequency figure 16. open loop voltage gain and phase versus frequency figure 17. normalized gain bandwidth product versus temperature figure 18. percent overshoot versus load capacitance figure 19. phase margin versus load capacitance 1.0 10 100 1.0 k 100 k 1.0 m 10 m 100 m 10 k f, frequency (hz) vol a, open loop voltage gain (db) phase gain , excess phase (degrees) f solid line curves compensated units dashed line curves decompensated units v cc /v ee = 15 v v o = 0 v r l = 2.0 k t a = 25 c 1.0 2.0 3.0 5.0 7.0 10 20 30 50 f, frequency (hz) 1 2 3 4 , excess phase (degrees) f 1 gain, r l = 2.0 k 2 gain, r l = 2.0 k, c l = 100 pf 3 phase, r l = 2.0 k 4 phase, r l = 2.0 k, c l = 100 pf compensated units only v cc /v ee = 15 v v o = 0 v t a = 25 c phase margin = 54 gain margin = 7.6 db 1.0 2.0 3.0 5.0 7.0 10 20 30 50 f, frequency (hz) -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) gbw, gain bandwidth product (normalized) v cc /v ee = 15 v r l = 2.0 k 10 100 1.0k c l , load capacitance (pf) percent overshoot v cc /v ee = 15 v r l = 2.0 k d v o = 100 mv pp v o = -10 v to +10 v t a = 25 c decompensated units a v = +2.0 compensated units a v = +1.0 10 100 1.0k c l , load capacitance (pf) v cc /v ee = 15 v r l = 2.0 k to d v o = 100 mv pp v o = -10 v to +10 v t a = 25 c decompensated units a v = +2.0 compensated units a v = +1.0 m f , phase margin (degrees) , excess phase (degrees) f vol a, open loop voltage gain (db) vol a, open loop voltage gain (db) 100 80 60 40 20 0 20 10 0 -10 -20 -30 -40 20 10 0 -10 -20 -30 -40 1.20 1.10 1.00 0.90 0.80 100 80 60 40 20 0 70 60 50 40 30 20 10 0 100 120 140 160 180 200 100 120 140 160 180 200 0 45 90 135 180
mc34080 thru mc34085 http://onsemi.com 8 solid line curves-compensated units a v = +1.0 dashed line curves-decompensated units a v = +2.0 v cc /v ee = 15 v r l = 2.0 k to d v o = 100 mv pp v o = -10 v to +10 v c l = 10 pf c l = 200 pf c l = 360 pf c l = 100 pf figure 20. gain margin versus load capacitance figure 21. phase margin versus temperature figure 22. gain margin versus temperature figure 23. normalized slew rate versus temperature 10 100 10 k c l , load capacitance (pf) a, gain margin (db) m v cc /v ee = 15 v r l = 2.0 k to d v o = 100 mv pp v o = -10 v to +10 v t a = 25 c compensated units a v = +1.0 decompensated units a v = +2.0 -55 -25 0 25 50 75 100 125 m t a , ambient temperature ( c) f , phase margin (degrees) c l = 10 pf c l = 360 pf c l = 200 pf solid line curves-compensated units a v = +1.0 dashed line curves-decompensated units a v = +2.0 v cc /v ee = 15 v r l = 2.0 k to d v o = 100 mv pp v o = -10 v to +10 v c l = 100 pf -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) sr, slew rate (normalized) -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) v cc /v ee = 15 v a v = +1.0 for compensated units a v = -1.0 for decompensated units r l = 2.0 k c l = 100 pf v o = -10 v to +10 v a, gain margin (db) m 10 8.0 6.0 4.0 2.0 0 60 50 40 30 20 10 0 10 8.0 6.0 4.0 2.0 0 1.40 1.20 1.00 0.80 0.60
mc34080 thru mc34085 http://onsemi.com 9 mc34084 transient response a v = +1.0, r l = 2.0 k, v cc /v ee = 15 v, t a = 25 c figure 24. small signal figure 25. large signal mc34085 transient response a v = +2.0, r l = 2.0 k, v cc /v ee = 15 v, t a = 25 c figure 26. small signal figure 27. large signal 0 0 0 0 0.2 m s/div 0.5 m s/div 0.2 m s/div 0.5 m s/div 50 mv/div 5.0 mv/div 50 mv/div 5.0 mv/div c l = 10 pf c l = 10 pf c l = 100 pf c l = 100 pf
mc34080 thru mc34085 http://onsemi.com 10 t a = 125 c t a = 25 c t a = -55 c supply current normalized to v cc /v ee = 15 v, t a = 25 c r l = v o = 0 t a = 25 c figure 28. common mode rejection ratio versus frequency figure 29. power supply rejection ratio versus frequency figure 30. power supply rejection ratio versus temperature figure 31. normalized supply current versus supply voltage figure 32. channel separation versus frequency figure 33. spectral noise density 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m cmrr, common mode rejection ratio (db) f, frequency (hz) v cc /v ee = 15 v d v s = 3.0 v v o = 0 v t a = -55 c t a = 125 c 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m f, frequency (hz) pssr, power supply rejection ratio (db) v cc /v ee = 15 v d v s = 3.0 v v o = 0 v t a = 25 c positive supply negative supply compensated units a v = +1.0 decompensated units a v = +2.0 v cc /v ee = 15 v d v s = 3.0 v v o = 0 v f 10 hz positive supply negative supply -55 -25 0 25 50 75 100 125 pssr, power supply rejection ration (db) t a , ambient temperature ( c) 0 5.0 10 15 20 25 i, supply current (normalized) cc v s , supply voltage (v) 10 k 100 k 1.0 m 10 m channel seperation (db) f, frequency (hz) v cc /v ee = 15 v t a = 25 c 10 k 100 k 10 100 1.0 k e, input noise voltage ( n f, frequency (hz) nv/ hz ) v cc /v ee = 15 v v cm = 0 t a = 25 c compensated units a v = +1.0 decompensated units a v = +2.0 100 80 60 40 20 0 120 100 80 60 40 20 0 110 100 90 80 70 1.20 1.10 1.00 0.90 0.80 0.70 120 100 80 60 40 20 0 100 80 60 40 20 0 v cc d v cc + v o - v cc d v cc v ee d v ee + v o - v cc d v cc v ee d v ee + v o - v ee d v ee
mc34080 thru mc34085 http://onsemi.com 11 applications information the bandwidth and slew rate of the mc34080 series is nearly double that of currently available general purpose jfet opamps. this improvement in ac performance is due to the pchannel jfet differential input stage driving a compensated miller integration amplifier in conjunction with an all npn output stage. the all npn output stage offers unique advantages over the more conventional npn/pnp transistor class ab output stage. with a 10 k load resistance, the op amp can typically swing within 1.0 v of the positive rail (v cc ), and within 0.3 v of the negative rail (v ee ), providing a 28.7 pp swing from 15 v supplies. this large output swing becomes most noticeable at lower supply voltages. if the load resistance is referenced to v cc instead of ground, the maximum possible output swing can be achieved for a given supply voltage. for light load currents, the load resistance will pull the output to v cc during the positive swing and the npn output transistor will pull the output very near v ee during the negative swing. the load resistance value should be much less than that of the feedback resistance to maximize pullup capability. the all npn transistor output stage is also inherently fast, contributing to the operation amplifier's high gainbandwidth product and fast settling time. the associated high frequency output impedance is 50 w (typical) at 8.0 mhz. this allows driving capacitive loads from 0 pf to 300 pf without oscillations over the military temperature range, and over the full range of output swing. the 55 c phase margin and 7.6 db gain margin as well as the general gain and phase characteristics are virtually independent of the sink/source output swing conditions. the high frequency characteristics of the mc34080 series is especially useful for active filter applications. the common mode input range is from 2.0 v below the positive rail (v cc ) to 4.0 v above the negative rail (v ee ). the amplifier remains active if the inputs are biased at the positive rail. this may be useful for some applications in that single supply operation is possible with a single negative supply. however, a degradation of offset voltage and voltage gain may result. phase reversal does not occur if either the inverting or noninverting input (or both) exceeds the positive common mode limit. if either input (or both) exceeds the negative common mode limit, the output will be in the high state. the input stage also allows a differential up to 44 v, provided the maximum input voltage range is not exceeded. the supply voltage operating range is from 5.0 v to 22 v. for optimum frequency performance and stability, careful component placement and printed circuit board layout should be exercised. for example, long unshielded input or output leads may result in unwanted inputoutput coupling. in order to reduce the input capacitance, resistors connected to the input pins should be physically close to these pins. this not only minimizes the input pole for optimum frequency response, but also minimizes extraneous apickupo at this node. supply decoupling with adequate capacitance close to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit large impedance changes over temperature. primarily due to the jfet inputs of the op amp, the input offset voltage may change due to temperature cycling and board soldering. after 20 temperature cycles ( 55 to 165 c), the typical standard deviation for input offset voltage is 559 m v in the plastic packages. with respect to board soldering (260 c, 10 seconds), the typical standard deviation for input offset voltage is 525 m v in the plastic package. socketed devices should be used over a minimal temperature range for optimum input offset voltage performance. 3 2 4 1 5 6 7 + - 5.0 k v cc v ee figure 34. offset nulling circuit
mc34080 thru mc34085 http://onsemi.com 12 p suffix plastic package case 62605 issue k d suffix plastic package case 75105 (so8) issue r outline dimensions notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.18 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeters. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include mold protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10
mc34080 thru mc34085 http://onsemi.com 13 p suffix plastic package case 64606 issue l outline dimensions notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 dw suffix plastic package case 751g02 (so16l) issue a dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k
mc34080 thru mc34085 http://onsemi.com 14 notes
mc34080 thru mc34085 http://onsemi.com 15 notes
mc34080 thru mc34085 http://onsemi.com 16 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc34080/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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